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Dual RF LDMOS Bias Controllers
with I 2 C/SPI Interface
Table 19. SCLR (Write)
BIT NAME
X
FULLRESET
DATA BIT
D15–D10
D9
POR
X
N/A
FUNCTION
Don’t care
Full reset of all DAC registers is a two write operation:
1) FULLRESET = 0, ARMRESET = 1
ARMRESET
X
CLFIFO
HIGHCL2
LOWCL2
FINECL1
HIGHCL1
LOWCL1
FINECL2
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
X
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2) FULLRESET = 1, ARMRESET = 0
Don’t care
1 = Clear FIFO and FIFO flag bits
0 = Do not clear FIFO or FIFO flag bits
1 = Reset coarse DAC2 high wiper to its POR state
0 = Do not reset coarse DAC2 high wiper to its POR state
1 = Reset coarse DAC2 low wiper to its POR state
0 = Do not reset coarse DAC2 low wiper to its POR state
1 = Reset fine DAC1 to its POR state
0 = Do not reset fine DAC1 to its POR state
1 = Reset coarse DAC1 high wiper to its POR state
0 = Do not reset coarse DAC1 high wiper to its POR state
1 = Reset coarse DAC1 high wiper to its POR state
0 = Do not reset coarse DAC1 high wiper to its POR state
1 = Reset fine DAC2 to its POR state
0 = Do not reset fine DAC2 to its POR state
Wiper Input register by sending the appropriate read
command byte.
FINETHRUCAL1 and FINETHRUCAL2 (Write)
Write to the Fine DAC1/DAC2 Write-Through Input reg-
ister with autocalibration by sending the appropriate
write command byte followed by data bits D15–D0 (see
Table 22). Bits D15–D10 are don’t care. A write to these
registers not only triggers the autocalibration but imme-
diately updates the output of the DAC by transferring
the DAC input register with correction code to the Fine
DAC output register. POR contents for these registers
are all zeros. Read the DAC Input register values writ-
ten to Fine DAC1 and DAC2 Input registers through the
Fine DAC1/DAC2 Input Read register. These read reg-
isters contain the latest user-write to any Fine DAC1 or
Fine DAC2 Input register and do not contain autocali-
bration-corrected values.
FIFO (Read)
Read the oldest result in the FIFO by sending the
appropriate read command byte and reading out data
bits D15–D0 (see Table 23). Bits D15–D12 are channel
tag bits that indicate the source of the conversion. Bits
D11–D0 contain the conversion result. Reading from
the FIFO when the FIFO is empty results in the current
contents of the Flag read register to be sent.
RDFINE1 and RDFINE2 (Read)
Read the Fine DAC1/DAC2 Input Read register by
sending the appropriate read command byte and read-
ing out data bits D15–D0 (see Table 24). Data contains
the last write to any Fine DAC1/DAC2 Input registers
and does not contain autocalibration-corrected values.
RDFLAG (Read)
The Flag register contains important system information
regarding ADC/FIFO status and alarm conditions. Read
the Flag register by sending the appropriate read com-
mand byte and reading out data bits D15 –D0 (see
Table 25). Bits D15–D12 are don’t care. ADCBUSY is
set to 1 when the ADC is busy, an ALARM value is
being checked, or the ADC results are being loaded
into the FIFO. ADCBUSY is set to 0 when the ADC has
completed all the conversions in the current scan.
ALUBUSY is set to 1 when the ALU is busy and set to 0
when it is not. ALUBUSY is set to 1 for 134μs at power-
up for initialization. FIFOEMP is set to 1 when the FIFO
is empty and set to 0 when the FIFO contains data.
Writing to the appropriate bit in the Software Clear reg-
ister empties the FIFO and sets the FIFOEMP bit to 1.
______________________________________________________________________________________
37
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